1. Field of the Invention
The present invention relates to a method of production of a semiconductor device, more particularly relates to a method of production of a wafer level package.
2. Description of the Related Art
As a method of production of a semiconductor device, there is the method of forming insulating layers, interconnect patterns, external electrode terminals, etc. on the surface of a semiconductor wafer at the stage of the semiconductor wafer where semiconductor chips are formed arranged in predetermined defined arrangements, and finally dicing the semiconductor wafer into individual pieces so as to produce chip-sized semiconductor devices (wafer level package). Japanese Unexamined Patent Publication (Kokai) No. 2002-93942 describes a method of production of a semiconductor device comprising forming a reinterconnect layer at the surface of the semiconductor wafer where the electrode terminals are formed, forming a reinterconnect layer on the back side of a semiconductor chip from the semiconductor chip side, and forming external terminals electrically connected with the electrode terminals.
Japanese Unexamined Patent Publication (Kokai) No. 2002-134651 describes a method of production of a semiconductor device comprising forming connection bumps on electrode terminals of a semiconductor wafer, then covering the surface on which the connection bumps are formed by a resin so that the end faces of the connection bumps are exposed and further covering the back side of the semiconductor wafer by a resin. Further, Japanese Unexamined Patent Publication (Kokai) No. 2002-270720 describes a method of production of a semiconductor device comprising forming projecting electrodes on electrode pads of the surfaces of the semiconductor chips of the semiconductor wafer, covering the surface of the semiconductor wafer by an insulating resin so that the projecting electrodes are exposed, grinding the back side of the semiconductor wafer, then covering the back side of the semiconductor wafer by an insulating resin, and dicing the semiconductor wafer to obtain the individual semiconductor devices.
In the above conventional methods of production of wafer level packages, sputtering etc. are used to form a film on or expose the semiconductor wafer to produce a semiconductor device. Therefore, production of such a product required use of expensive production systems such as film-forming systems or exposure systems. In particular, when using a 300 mm (12 inch) large-sized semiconductor wafer, for which it is considered use will increase, to produce a semiconductor package, it is necessary to construct a new production system, but there is the problem that new investment is necessary.
A wafer level package has a thermal expansion coefficient substantially equal to the thermal expansion coefficient of the silicon material of a semiconductor wafer, so when mounting a wafer level package on a resin board (mounting circuit board) made of a resin usually used for a mounting circuit board, the thermal expansion coefficient greatly differs from the resin board, so there is the problem that heat stress acts on the connecting parts of the wafer level package and resin board (solder balls) and the connecting parts crack. Accordingly, the products previously provided as wafer level packages were limited to small products of a size of not more than 10 mm square or so. Further, in conventional wafer level packages, sometimes the silicon material of the semiconductor wafer was left exposed to the outside in the product. With such a product, the package is insufficiently protected. Further, the back side is not electrically insulated, so electrical short-circuits occur at the back side of the package.